module fw_pipe #(
	parameter WIDTH = 8)
(
	input clk,
	input rst_n,
	
	input [WIDTH -1:0]data_in,
	input 			  data_in_valid,
	output			  data_in_ready,
	
	output[WIDTH -1:0]data_out,
	output			  data_out_valid,
	input			  data_out_ready
);

wire in_valid_en = data_in_ready;
wire in_valid_d  = data_in_valid;
wire in_valid_q;
dffre #(.WIDTH(1))
u_in_valid_dffre(
	.clk(clk),
	.rst_n(rst_n),
	.d(in_valid_d),
	.en(in_valid_en),
	.q(in_valid_q)
);

wire 			 data_en = data_in_valid && data_in_ready;
wire [WIDTH -1:0]data_d  = data_in;
wire [WIDTH -1:0]data_q;
dffe #(.WIDTH(WIDTH))
u_in_data_dffe(
	.clk(clk),
	.d(data_d),
	.en(data_en),
	.q(data_q)
);

assign data_in_ready  = data_out_ready || (~in_valid_q);
assign data_out_valid = in_valid_q;
assign data_out = data_q;

endmodule
